The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a chemical-mechanical polishing (CMP) process utilized in semiconductor manufacturing.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation.
As IC technology has moved from 130 nanometers (nm) to 90 nm and beyond, planarizing techniques, such as chemical-mechanical polishing (CMP), are required to selectively remove high elevation features by a combination of mechanical polishing and chemical reaction. A typical system for CMP may have one or more platens, each for performing a separate CMP process. Generally, a wafer is mounted on a rotating carrier, and a CMP process is performed at each platen. Typically, an abrasive-containing aqueous slurry is provided during CMP to facilitate the process.
Several techniques have been used to advance the results of CMP. For example, oxide device reverse (ODR) is often used to remove a significant amount of oxide on large active areas. ODR requires more extra process steps and a mask (referred to as an ODR mask), and still could benefit from better thickness control. Another example is to use a high selectivity slurry (HSS) for a direct CMP procedure. In comparison with conventional silica-based slurries, the utilization of a HSS results in superior within-wafer (WIW) uniformity of trench oxide and active Si3N4 thickness, and superior within-die (WID) uniformity of trench oxide and active Si3N4 thickness. However, the utilization of HSS also results in increased scratch rates on the wafer, and therefore high defect rates.
What is desired is a new and improved system and method for enhancing the CMP process.